X86

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x86 is a family of architecture-based instruction set that is backward-compatible based on Intel 8086 CPU and its Intel 8088 variant. The 8086 was introduced in 1978 as a full 16-bit extension of an 880-bit Intel 8-bit microprocessor, with memory segmentation as a solution to handle more memory than can be covered by a plain 16-bit address. The term "x86" came about because the names of some of the successors of Intel 8086 processors ended in "86", including 80186, 80286, 80386 and 80486 processors.

Many additions and extensions have been added to the x86 instruction set for years, almost consistent with full backwards compatibility. The architecture has been implemented in processors from Intel, Cyrix, AMD, VIA and many other companies; there are also open implementations, such as the Zet SoC platform. Nevertheless, from them, only Intel, AMD, and VIA are licensed x86 architectures, and produce a modern 64-bit design.

The term is not identical to IBM PC compatibility, as it implies a lot of other computer hardware; embedded systems, and general-purpose computers, using x86 chips before PC-compatible markets started, some of them before the IBM PC (1981) itself.

By 2018, most personal computers and laptops sold are based on x86 architectures, while other categories - particularly high-volume mobile categories such as smartphones or tablets - are dominated by ARM; on the high end, x86 continues to dominate intensive computing computing and computing network computing.

Video X86

Ikhtisar

In the 1980s and early 1990s, when the 8088 and 80286 were still in common use, the term x86 usually represented a compatible 8086 CPU. Today, however, x86 usually implies binary compatibility as well with a 32-bit instruction set of 80386. This is due to the fact that this instruction set has become something of the lowest common denominator for many modern operating systems and possibly also because the term became common after the introduction of 80386 in 1985.

A few years after the introduction of 8086 and 8088, Intel added some complexity to the scheme and its naming terminology as "iAPX" from an ambitious but poorly administered iAPX 432 Intel processor on more than 8086 chip families, implemented as a sort of system-level prefix. 8086 system , including coprocessors such as 8087 and 8089, as well as simpler specific Intel system chips, thus described as iAPX 86 . There are also terms for iRMX (for operating systems), iSBC (for single board computers), and iSBX (for multimodule boards based on 8086-architecture) Ã, - all together under the title Microsystem 80 . However, this naming scheme is temporary enough, which lasted for several years during the early 1980s.

Although the 8086 was primarily developed for embedded systems and multi-user or single-user computers, mostly in response to compatible Zilog Z80 8080, the x86 line soon grew in features and processing power. Today, x86 is everywhere both on stationary and portable personal computers, and is also used in midrange computers, workstations, servers and most new supercomputer sets from the TOP500 list. A large number of software, including a large list of x86 operating systems using x86-based hardware.

Modern x86 is relatively rare in embedded systems, however, and small low power applications (using small batteries) as well as inexpensive microprocessor markets, such as home appliances and toys, do not have significant x86 presence. The 8-bit Wikipedia and 16-bit based architecture are common here, although x86-compatible VIA C7, VIA Nano, AMD Geode, Athlon Neo and Intel Atom are examples of 32- and 64-bit designs used in some relative low power and low cost segment.

There have been several attempts, including by Intel itself, to end the dominance of the "odd" x86 architecture market designed directly from the first simple 8-bit microprocessor. An example is the iAPX 432 (project originally named "Intel 8800"), Intel 960, Intel 860, and Intel Itanium/Hewlett-Packard architecture. However, the continuous refinement of the x86 microarchitecture, circuitry and semiconductor manufacturing will make it difficult to replace x86 in many segments. The 64-bit AMD extension of x86 (eventually perceived by Intel with compatible design) and x86 chip scalability like Intel Xeon eight-core and 12-core AMD Opteron underscore x86 as an example of how continuous refinement of industry standards can resist competition from architecture totally new.

Maps X86

Chronology

The table below lists models of processors and model series that apply variations of the x86 instruction set, in chronological order. Each line item is marked with a significantly enhanced or commercially successful microarchitecture architecture design.

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History

Other manufacturers

At various times, companies such as IBM, NEC, AMD, TI, STM, Fujitsu, OKI, Siemens, Cyrix, Intersil, C & T, NexGen, UMC, and DM & amp; P started designing or producing x86 processors (CPUs) intended for personal computers as well as embedded systems. Such x86 implementations are rarely a simple copy but often use different internal microarchitectures as well as different solutions at the electronic and physical levels. Quite naturally, the initial compatible microprocessor is 16-bit, while the 32-bit design is developed much later. For the personal computer market, real quantities began to emerge around 1990 with i386 and i486 compatible processors, often called similar to native Intel chips. Other companies, which design or produce x86 or x87 processors, include ITT Corporation, National Semiconductor, ULSI System Technology, and Weitek.

Following the fully pipelined i486, Intel introduced the Pentium brand name (which, unlike numbers, could become a trademark) for their new superscalar x86 design suite; with the x86 naming scheme now legally cleared, other x86 vendors had to choose a different name for x86 compatible products, and initially some chose to proceed with a variation of the numbering scheme: IBM partnered with Cyrix to generate 5x86 and then very efficiently Line 6x86 ( M1) and 6x86MX (MII) from the Cyrix design, which is the first x86 microprocessor to apply register name changes to allow speculative execution. Meanwhile AMD designs and manufactures sophisticated but delayed 5k86 (K5), which, internally , is very closely based on the previous draft RISC 29K AMD; Similar to NexGen Nx586, it uses the strategy in such a way that the special pipeline stages describe x86 instructions into uniform and handy micro operations, a method that remains the basis for most x86 designs to date.

Some early versions of this microprocessor have heat dissipation problems. The 6x86 is also affected by some minor compatibility issues, the Nx586 has no floating point units (FPU) and (crucial) pin-compatibility, while K5 has a rather disappointing performance when it (finally) is introduced. Customer ignorance about alternatives to the Pentium series further contributed to this design being relatively unsuccessful, despite the fact that the K5 has excellent Pentium compatibility and 6x86 is significantly faster than Pentium on integer code. AMD later succeeded in establishing itself as a serious competitor with the K6 processor set, which gave way to the highly successful Athlon and Opteron. There are also other competitors, such as Centaur Technology (formerly IDT), Rise Technology, and Transmeta. The energy-efficient C3 and C7 process VIA Technologies, designed by the Centaur company, has been sold for years. Centaur's latest design, VIA Nano, is their first processor with superscalar and speculative execution. That, perhaps interestingly, was introduced at about the same time as Intel's first "in-order" processor since the P5 Pentium, Intel Atom.

Word size extensions

The instruction set architecture has twice expanded to a larger word size. In 1985, Intel released the 32-bit 80386 (later known as i386) which gradually replaced the previous 16-bit chips on the computer (though usually not in embedded systems) during the following years; This extended programming model was originally referred to as i386 architecture (like the first implementation) but Intel was later dubbed IA-32 when it introduced the (unrelated) IA-64 architecture.

In 1999-2003, AMD expanded the 32-bit architecture to 64 bit and referred to it as x86-64 in the initial document and then as AMD64. Intel soon adopted the AMD architecture extension under the name IA-32e, then used the EM64T name and eventually used Intel 64. Microsoft and Sun Microsystems/Oracle also use the term "x64", while many Linux distributions, and BSD also use the term "amd64". Microsoft Windows, for example, designates its 32-bit version as "x86" and 64-bit versions as "x64", while 64-bit versions of Windows installation files are required to be placed into a directory named "AMD64".

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Overview

Basic architectural properties

The x86 architecture is variable length instruction, especially the "CISC" design with emphasis on backward compatibility. The instruction set is not typical of CISC, however, it is basically a long version of a simple 8808 and 8080 architecture. Byte-addressing is enabled and words are stored in memory with little-endian byte order. Memory access to unaligned addresses is allowed for all valid sizes of words. The largest original size for integer arithmetic and memory addresses (or offsets) is 16, 32 or 64 bit depending on architectural generation (newer processors include direct support for smaller integers as well). Multiple scalar values ​​can be handled simultaneously through existing SIMD units in the next generation, as described below. Direct addressing of offsets and direct data can be expressed as an 8-bit number for the case or context that often occurs where the range -128.127 is sufficient. Therefore, the instruction used is 2 or 3 bytes in length (although some are longer, and some are single bytes).

To further save the encoding space, most of the registers are expressed in opcodes using three or four bits, the last one being the opcode prefix in 64-bit mode, while at most one pass to the instruction can be a memory location. However, these memory operands can also be destination (or combined sources and destinations), while other operands, sources , can either list or soon . Among other factors, this contributes to code sizes that rival an eight-bit machine and allows efficient use of instruction cache memory. The relatively small number of registers (also inherited from the 8-bit ancestors) has made relative registering (using small direct offsets) an important method for accessing operands, especially on the stack. Therefore, much work has been invested in making such access as fast as the access list, which is throughput of a single-cycle instruction, in most circumstances where the data accessed is available in the top-level cache.

Floating point and SIMD

A special floating point processor with 80-bit internal registers, 8087, developed for the original 8086. The microprocessor was then developed into an expanded 80387, and then the processor combines compatible versions compatible with this functionality on the same microprocessor as the main processor.. In addition, the modern x86 design also contains a SIMD unit (see SSE below) where instructions can work in parallel on (one or two) 128-bit words, each containing two or four floating point numbers (64 or 32 bits wide each), or alternatively, 2, 4, 8 or 16 integers (64, 32, 16 or 8 bits each width).

The presence of extensive SIMD registers means that existing x86 processors can load or store up to 128 bits of memory data in one instruction and also perform bitwise (though not integer arithmetic) operations on a full 128-bit number in parallel. Intel Sandy Bridge processors add AVX (Advanced Vector Extensions) instructions, widening the SIMD list to 256 bits. Knights Corner, the architecture that Intel uses on their Xeon Phi co-processor, uses a 512-bit wide SIMD list.

Current Implementation

During execution, the x86 processor currently uses some additional decode steps to divide most of the instructions into smaller sections called micro operations. This is then left to the control unit that buffers and schedules them according to x86-semantics so they can be executed, partially in parallel, by one of several execution units (more or less special). The modern x86 design is thus pipelined, superscalar, and also able to exit speculative orders and execution (through branch predictions, renaming registers, and memory dependency predictions), meaning they can run multiple x86 (partial or complete) instructions simultaneously, and not necessarily in the same order as given in the instruction stream. Intel and AMD CPUs (starting from AMD Zen) are also capable of multithreading simultaneously with two threads per core (Xeon Phi has four threads per core) and in the case of Intel transactional memory (TSX).

When introduced, in the mid-1990s, this method was sometimes referred to as the "RISC core" or as a "RISC translation", partly for marketing reasons, but also because these micro-operations share some properties with certain types of RISC instructions. However, the traditional microcode (used since the 1950s) also inherently shares many of the same properties; this new method differs mainly because translation to micro operations now takes place asynchronously. Not having to synchronize an execution unit with decode steps opens the possibility for more analysis of the code stream (buffered), and therefore allows detection of operations that can be performed in parallel, simultaneously feeding more than one executable unit.

The latest processors also do the opposite if appropriate; they combine a specific x86 sequence (such as a comparison followed by a conditional jump) into a more complex micro-op that matches a better execution model and thus can be executed faster or with fewer machine resources involved.

Another way to try to improve performance is to store the decoded micro-operations, so the processor can directly access the decoded micro-operations of the special cache, instead of parsing them again. Intel follows this approach with the Execution Trace Cache feature on the NetBurst Microarchitecture (for Pentium 4 processors) and later in the Decoded Stream Buffer (for Core branded processors since Sandy Bridge).

Transmeta uses a completely different method in their compatible x86 CPU. They use a just-in-time translation to convert x86 instructions to the original VLIW CPU instruction set. Transmeta argues that their approach allows for a more efficient design of power because the CPU can forget the complicated decode steps of a more traditional x86 implementation.

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Segmentation

Minicomputers during the late 1970s were running against the 64-KB 64-bit address limit, because memory had become cheaper. Some minikomputers like the PDP-11 use a complex bank transfer scheme, or, in the case of VAX Digital, redesign a much more expensive processor that can directly handle addressing and 32-bit data. The original 8086, developed from a simple 8080 microprocessor and is primarily intended for very small and inexpensive computers and other specialized devices, instead adopts a simple segment register that increases the memory address width by just 4 bits. By multiplying the 64-KB address by 16, the 20-bit address can handle a massive one megabyte (1,048,576 bytes) large enough for a small computer at the time. The segment register concept is not new to many mainframes that use segment registers to swap quickly to different tasks. In practice, on x86 it is a widely criticized implementation of a very complicated many common programming tasks and compilations. However, the architecture soon enabled the 32-bit linear addressing (starting with 80386 at the end of 1985) but main actors (like Microsoft) took several years to change their 16-bit based system. 80386 (and 80486) are therefore mostly used as a fast (but still 16-bit) 8086 for many years.

The data and code can be managed in a "near" 16-bit segment in 64Ã, KB part of the total 1 MB address space, or the compiler can operate in "remote" mode using 32-bit segment: offset (only) 1 MB. While it would also prove quite limiting in the mid-1980s, it worked for the emerging PC market, and made it very easy to translate software from older 8008, 8080, 8085, and Z80 to newer processors. During 1985, the 16-bit segment addressing model was effectively taken into account by the introduction of 32-bit offset registers, in the 386 design.

In real mode, segmentation is achieved by shifting the segment address left by 4 bits and adding the offset to receive the last 20-bit address. For example, if DS is A000h and SI is 5677h, DS: SI will refer to the absolute address DS ÃÆ'â € "10h SI = A5677h. Thus the total address space in real mode is 2 ²⁰ bytes, or 1 MB, a number quite impressive for 1978. All memory addresses consist of segments and offsets; each access type (code, data, or stack) has a list of default segments associated with it (for DS register data, for that code is CS, and for that stack it is SS). For data access, segment registers can be explicitly specified (using the segment override prefix) to use one of the four segment registers.

In this scheme, two distinct segment/offset pairs can point to an absolute location. So if DS is A111h and SI 4567h, DS: SI will refer to the same A5677h as above. This scheme makes it impossible to use more than four segments at once. CS and SS are essential for proper functioning of the program, so only DS and ES can be used to point to data segments outside of the program (or, more precisely, outside the executed program segment) or stack.

In protected mode, introduced in 80286, segment registers no longer contain the initial physical address of the segment, but contain "selectors" that point to a system-level structure called segment descriptor . The segment descriptor contains the initial physical address of the segment, the length of the segment, and the access permissions to that segment. The offset is checked against the length of the segment, with offsets referring to locations outside the segment causing exceptions. Offsets referring to locations within a segment are combined with the initial physical address of the segment to obtain the physical address corresponding to the offset.

Segmented properties can make programming and compiler design harder because pointers that are close and far affect performance.

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Addressing mode

The relative instruction handles in 64-bit code (RIP displacement, where RIP is the instruction pointer register) simplifies the implementation of position-independent code (as used in shared libraries across multiple operating systems).

8086 has 64Ã, KB of the eight-bit (or alternate 32Ã, K-word of 16-bit ) I/O space, and 64Ã, KB (one segment) stack in memory supported by computer hardware. Only words (two bytes) can be pushed onto the stack. The stack grows to a lower address numerically, with SS: SP pointing to the most recently driven item. There are 256 interruptions, which can be called by hardware and software. The interrupt can flow, using the stack to save the sender's address.

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register x86

16-bit

The original Intel 8086 and 8088 had fourteen 16-bit registers. Four of them (AX, BX, CX, DX) are general-purpose registers (GPR), although each can have an additional purpose; for example, only CX can be used as a counter with the loop instruction. Each can be accessed as two separate bytes (so a high BX byte can be accessed as a BH and a low byte as a BL). Two pointer registers have a special role: SP (stack pointer) points to "top" of the stack, and BP (pointer base) is often used to point to some other place on the stack, usually above the local variable (see frame pointer). ). Register SI, DI, BX and BP are address registers, and can also be used for indexing arrays.

Four segment registers (CS, DS, SS and ES) are used to form memory addresses. The FLAGS registers contain flags such as carrying flags, overflow flags and zero flags. Finally, the instruction pointer (IP) points to the next instruction to be retrieved from memory and then executed; this list can not be accessed directly (read or written) by a program.

Intel 80186 and 80188 are essentially an enhanced 8086 or 8088 CPU, respectively, with on-chip peripherals added, and they have the same CPU registers as 8086 and 8088 (in addition to the peripheral register interface).

8087, 8088, 80186, and 80188 can use an optional floating-point coop, 8087. 8087 appears to the programmer as part of the CPU and adds eight 80-bit wide registers, st (0) to st (7), each can store numerical data in one of seven formats: 32-, 64-, or 80-bit floating point, 16-, 32-, or 64-bit (binary) integers, and an 80-bit decimal integer.

On Intel 80286, to support protected mode, three special registers store the descriptor table address (GDTR, LDTR, IDTR), and the fourth task register (TR) is used for task shifting. 80287 is a floating-point coprocessor for 80286 and has the same register as 8087 with the same data format.

32-bit

With the advent of 32-bit 80386 processors, 16-bit general-purpose registers, base registers, index registers, instruction pointers, and FLAGS registers, but not segment registers, expanded to 32 bits. The nomenclature represents this with the prefix " E " (for "extended") to the list name in the x86 assembly language. Thus, the AX register corresponds to the lowest 16 bit of the new 32-bit EAX register, SI corresponds to the lowest 16 ESI bit, and so on. Public registers, base registers, and index registers can all be used as bases in addressing modes, and all registers except the stack pointer can be used as indexes in addressing modes.

Two new segment registers (FS and GS) are added. With more number of registers, instructions, and operands, the machine code format is expanded. To provide backward compatibility, segments with executable code can be marked as containing 16-bit or 32-bit instructions. Specific prefixes allow for inclusion of 32-bit instructions in 16-bit segments or otherwise .

80386 has an optional floating-point co-processor, 80387; it has eight 80-bit wide registers: st (0) to st (7), such as 8087 and 80287. 80386 can also use 80287 processor. With 80486 and all subsequent x86 models, the floating point-point processing unit (FPU) is integrated on the chip.

Pentium MMX adds eight 64-bit MMX integer registers (MMX0 to MMX7, which share lower bits with 80-bit-wide FPU stack). With the Pentium III, Intel added 32-bit Streaming SIMD Extensions (SSE) control/status registers (MXCSR) and eight 128-bit SSE floating point registers (XMM0 to XMM7).

64-bit

Starting with an AMD Opteron processor, the x86 architecture extends the 32-bit register into 64-bit registers in a manner similar to how the 16 to 32-bit extension takes place. An R -prefix identifies a 64-bit register (RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP), and eight additional 64-bit common registers (R8- R15 ) was also introduced in the creation of x86-64. However, this extension can only be used in 64-bit mode, which is one of only two modes available only in long mode. Addressing modes do not change dramatically from 32-bit mode, except that addressing is expanded to 64 bits, virtual addresses are now marked extended to 64 bits (to disallow mode bits in virtual addresses), and other voter details are dramatically reduced. Additionally, addressing modes are added to allow reference memory relative to RIP (instruction pointer), to facilitate the application of position-independent code, used in shared libraries across multiple operating systems.

128-bit

SIMD mendaftarkan XMM0-XMM15.

256-bit

SIMD registered YMM0-YMM15.

512-bit

SIMD mendaftarkan ZMM0-ZMM31.

Miscellaneous/tujuan khusus

x86 processors that have protected mode, the 80286 processor and later, also have three register descriptors (GDTR, LDTR, IDTR) and task list (TR).

The 32-bit x86 processor (starting with 80386) also includes various special/miscellaneous registers such as control registers (CR0 to 4, CR8 for 64-bit only), debug registers (DR0 to 3, plus 6 and 7), test registers (TR3 up to 7; 80486 only), and a special register model (MSR, appears with Pentium).

Destination

Although the main register (with the exception of instruction pointer) is a "general purpose" in 32-bit and 64-bit versions of the instruction set and can be used for anything, it was originally envisaged that they were used for the following purposes:

• AL/AH/AX/EAX/RAX: Accumulator
• BL/BH/BX/EBX/RBX: The base index (for use with arrays)
• CL/CH/CX/ECX/RCX: Counters (for use with loops and strings)
• DL/DH/DX/EDX/RDX: Extend the accumulator's accuracy (eg join 32-bit EAX and EDX for 64-bit integer operations in 32-bit code)
• SI/ESI/RSI: The source index for string operations.
• IN/EDI/RDI: Destination index for string operations.
• SP/ESP/RSP: The stack pointer for the top address of the stack.
• BP/EBP/RBP: Stack base pointer to hold the current frame stack address.
• IP/EIP/RIP: Instruction instructions. Grasp the program counter, the current instruction address.

Register segmen:

• CS: Kode
• DS Tanggal
• SS: Stack
• ES: Data ekstra
• FS: Extra Data # 2
• GS: Extra Data # 3

There is no special purpose imaginable for 8 other registers available only in 64-bit mode.

Some instructions compile and execute more efficiently when using these registers for their designed purpose. For example, using AL as an accumulator and adding a direct byte value for it produces efficiently add to AL opcode 04h, whereas using BL register generates generic and again add to register opcode of 80C3h. Another example is the division of double precision and multiplication that works specifically with the AX and DX registers.

Modern compilers benefit from the introduction of sib bytes ( index-byte-base-index ) that allows registers to be treated uniformly (such as minicomputers). However, the use of the universal byte sib is not optimal, as it results in longer coding than just using it selectively when necessary. (The main benefit of your byte is the orthogonality and stronger addressing modes provided, allowing for storing instructions and the use of registers for address calculations such as index scaling.) Some special instructions lose priority in hardware design and become slower than small code sequences the equivalent. An important example is the LODSW instruction.

Structure

Note: The register? The PL is only available in 64-bit mode.

Note: The IL register is only available in 64-bit mode.

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Operation mode

Real mode

The Address Mode Actually, commonly called Real mode, is an operating mode of 8086 and then an x86-compatible CPU. Real mode is characterized by a segmented 20-bit memory address space (meaning only 1 MiB memory can be addressed - actually, a bit more), direct software access to peripheral hardware, and no concept of memory protection or multitasking at hardware level. All x86 CPUs are in 80286 series and then start in real mode when powered on; 80186 CPU and previously only had one operational mode, which is equivalent to real mode on the next chips. (On the IBM PC platform, direct software access to IBM BIOS routines is only available in real mode, since the BIOS is written for real mode, but this is not a characteristic of the x86 CPU but from the IBM BIOS design.)

To use more than 64 KB of memory, segment registers should be used. This creates major complications for implementers of compilers that introduce strange pointer modes such as "close," "remote" and "very large" to exploit the implicit properties of the segmented architecture to different degrees, with some pointers containing 16-bit offsets in the implied segments and others. pointer contains the segment and offset addresses in the segment. Technically it is possible to use up to 256 KB of memory for code and data, with up to 64 KB for code, by arranging the four segment registers once and then only using 16-bit offsets (optionally with prefix overriding default segments) to memory address, but this placing a substantial restriction on the way data can be addressed and memory operands can be combined, and that violates the architectural intentions of the Intel designers, who for separate data items (eg arrays, structures, unit codes) become contained in separate segments and handled by their own segment addresses , in a new program that is not ported from an earlier 8-bit processor with a 16-bit address space.

Protected mode

In addition to real mode, Intel 80286 supports shielded mode, extending the physical memory address to 16 MB and virtual memory that can be addressed to 1 GB, and provides protected memory, which prevents the program from destroying one another. This is done by using segment registers only to store the indexes to the descriptor tables stored in memory. There are two tables, the Global Descriptive Table (GDT) and the Local Descriptive Table (LDT), each with up to 8192 segment descriptions, each segment giving access to 64 KB of memory. In 80286, segment descriptor provides a 24-bit base address, and this base address is added to a 16-bit offset to create an absolute address. The base address of the table fulfills the same role that the literal value of the segment register satisfies in real mode; segment registers have been converted from direct registers to indirect registers. Each segment can be assigned one of the four ring levels used for hardware-based computer security. Each segment descriptor also contains a segment boundary field that determines the maximum offset that can be used with that segment. Since the offset is 16 bits, the segment is still limited to 64 KB each in 80286 protected mode.

Each time the segment register is loaded in protected mode, 80286 must read the 6-byte segment descriptor from memory to a set of hidden internal registers. Therefore, loading segment registers is much slower in protected mode than in real mode, and changing segments very often should be avoided. The actual memory operation using the protected mode segment is not slowed down much because the 80286 and then has the hardware to check offset against the segment boundary in parallel with the execution of the instruction.

The Intel 80386 extended offset and also segment boundary fields in each segment of 32 bit descriptor, allowing segments to reach the entire memory space. It also introduces support in unprotected mode for paging, a mechanism that allows to use paged virtual memory (with a 4 KB page size). Paging allows the CPU to map any page of the virtual memory space to any page of physical memory space. To do this, it uses an additional mapping table in memory called a page table. Protected mode on the 80386 can operate with either paging enabled or disabled; the segmentation mechanism is always active and generates a virtual address which is then mapped by the paging mechanism if enabled. The segmentation mechanism can also be disabled effectively by setting all segments to have base address 0 and size limits equal to the entire address space; it also requires a segment descriptor table of at least four descriptors (since FS and GS segments do not need to be used).

Paging is used extensively by modern multitasking operating systems. Linux, 386BSD and Windows NT were developed for 386 because it was the first Intel architecture CPU to support paging and 32-bit offset segments. Architecture 386 became the foundation of all further development in the x86 series.

x86 processor that supports boot-protected mode to real mode for backwards compatibility with an older 8086 class of processors. Once enabled (a.k.a. boot), the processor will initialize in real mode, and then start executing the instructions. The operating system boot code, which may be stored in ROM, can put the processor into protected mode to enable paging and other features. The instruction set is in protected mode similar to that used in real mode. However, certain constraints that apply to real modes (such as not being able to use axes, cx, dx in addressing) do not apply in protected mode. In contrast, the arithmetic segment, a common practice in real mode code, is not allowed in protected mode.

Virtual 8086 mode

There is also a sub-mode of operation in 32-bit protected mode (protected mode a.k.a. 80386) called virtual 8086 mode , also known as V86 mode . It's basically a special hybrid mode of operation that allows real-mode programs and operating systems to run temporarily under the control of protected supervisor mode operating systems. This allows a lot of flexibility in running both protected mode programs and real mode programs simultaneously. This mode is available exclusively for 32-bit protection mode; it's not in the 16-bit version of protected mode, or in long mode.

Long mode

Source of the article : Wikipedia